Gen-Z High-Performance Interconnect for the Data-Centric Future

Baden B

Current computer architectures allow for network and storage transfers to occur at much lower rates than memory transfers, so they must have separate buses, control signals, and command structures. Processors must wait endlessly for these transfers to finish or must find other work to do. A great deal of time is spent moving data between buffers to allow components working at highly different speeds to communicate effectively. Extra hardware is often needed to create DMA channels that perform transfers outside the normal flow of instructions and data. Resuming or cancelling partially completed transfers is difficult and error-prone.

Gen-Z is different. It is a high-bandwidth, low-latency fabric with separate media and memory controllers that can be realized inside or beyond traditional chassis limits. It treats all components as memory (so-called memory-semantic communications), and it moves data between them with minimal overhead and latency. It thus takes full advantage of emerging persistent memory (memory accessed over the data bus at memory speeds). It can also handle other compute elements, such as GPUs, FPGAs, and ASIC or coprocessor-based accelerators. There is no need for extra copy operations, special DMA channels, or complex error recovery schemes. The separate controllers allow separate scaling of processing, media, and memory. The end result is much higher throughput and much lower complexity for big data solutions in such applications as data analytics, deep packet inspection, artificial intelligence, machine learning, and video and image processing.

Gen-Z promotes innovation in multiple ways:

  • Gen-Z breaks the processor-memory interlock and enables new types of memory media to be transparently deployed at an accelerated rate.
  • Gen-Z supports a wide variety of component types including processors, memory modules, FPGAs, GPUs / GPGPUs, DSP, I/O, accelerators, NICs, custom ASICs, and many more.
  • Gen-Z supports a wide range of physical layer signaling rates and types (electrical and optical). This enables hardware to optimize performance while minimizing package costs, to scale to any bandwidth and distance within an enclosure or data center, and to provision multiple paths to provide aggregate performance and resiliency.
  • Gen-Z is processor agnostic. Solutions can be flexibly composed of any mix of processor types and capability. Further, Gen-Z specifies a common atomic protocol to ensure interoperability between any processor and any component type.
  • Gen-Z supports traditional processor-centric and new memory-centric solution architectures.
  • Gen-Z can be inserted into existing processor-centric solution architectures. This immediately enables any solution to reap Gen-Z’s benefits.
  • Gen-Z supports new memory-centric architectures, enabling any-to-any communication among all component types. Memory-centric architectures minimize data movement, reduce power consumption, reduce latency, and increase data access parallelism. Memory-centric architectures take advantage of Gen-Z multipath capabilities to increase aggregate performance and resiliency and enable new services
Liz Nardozza
Director of Technology and Architecture
He focuses on identifying pertinent new technologies and integrating them into Dell enterprise products. His current areas of interest include converged and hyperconverged systems, and accelerators for HPC, machine learning, and data analytics. Kurtis has over 25 years’ experience in the architecture, development, and business justification of server, storage, commercial, and consumer computing products. Before joining Dell, he held technical leadership positions at Panasas, a high-performance storage company, and Compaq. He earned a BSEE from New Mexico State University. Kurtis is submitting as president of and on behalf of the Gen-Z Consortium. The Gen-Z Consortium consists of leading computer industry companies dedicated to creating and commercializing a new open standard memory-oriented interface. The consortium’s members include Alpha Data, AMD, Amphenol Corporation, ARM, Broadcom, Cadence Design Systems, Cavium, Cray, Dell EMC, Everspin Technologies, FoxxConn Interconnect Technologies, HPE, Huawei R&D USA, IBM, IDT, IntelliProp, Jabil Circuit, Lenovo, Lotes, Luxshare-ICT, Mellanox Technologies, Mentor Graphics, Micron, Microsemi, Molex NetApp, Nokia, Numascale, PLDA Group, Red Hat, Samsung, Seagate, SK hynix, SMART Modular Technologies, Spin Transfer Technologies, TE Connectivity Corporation, Tyco Electronics (Shanghai) Co., Western Digital Technologies, Inc. (Sandisk), Xilinx, and YADRO Company.